The present invention relates to methods for analyzing integrated circuits (ICs) during design of the ICs or during failure analysis of those ICs during development. More particularly, present invention relates to a new and improved method of using new information derived from using an existing Verilog circuit simulation tool to develop input prediction information. The input prediction information is thereafter used in conjunction with an existing netlist definition of the circuit to define a cone or rearward extending group of only the relevant circuit components or cells of the IC which cause a particular output signal at a predetermined output signal transition time. Analysis of the IC is facilitated by reducing the amount of time and the tedium required for tracing the circuit in design and failure circumstances.
Most modern semiconductor integrated circuits (ICs) are extremely complex in the number and interconnection of their components or cells. The complexity results from a number of trends in modern electronics. For example, the continual miniaturization of ICs allows more functional cells to be placed on the same sized chip for essentially no additional cost. The cost of an IC is generally related only to the physical size of the substrate upon which the IC is formed and not to the number of components of the IC. Therefore, the effort is to include more cells and functionality in each new IC. The trend in electronics has also been toward integrating entire systems into a single chip, or at least toward integrating larger portions of entire systems into single chips. Such ICs are called application-specific integrated circuits (ASICs) or system level integrated circuits (SLICs).
Fabricating a modern, complex IC, such as an ASIC or SLIC, is also a complicated task. The fabrication involves designing the schematic circuitry by using specific cells and connecting them in certain manner, and then simulating the functionality of the schematic circuitry to determine whether the circuitry meets the desired functionality. The design and the simulation are so complex that both functions are generally performed by computer programs or tools designed for those specific purposes. For example, the circuit itself is designed by the use of a behavioral level language, which defines the all of cells in the circuit and their connectivity, and in doing so creates a file known as a netlist which describes those cells and their connectivity. A schematic viewing tool obtains information from the netlist to create a visual display of the circuit and its components. To test the functionality of the circuit, a Verilog simulation program is used. The Verilog simulation program refers to the netlist and additional information which defines the logical function and time delays and other functional factors associated with each of the cells, and develops output state change signals and output transition times for each of the cells in response to a specific input signal. The output state change signals and the output transition times for each of the cells is thereafter displayed by the use of a waveform viewing tool. The waveform viewing tool makes use of the output state change and transition time information derived from the Verilog simulation program to create a display of the waveforms existing at each of the cells in the circuit. The use of behavioral level language circuit synthesis tools and Verilog simulation tools is well-known.
The design and fabrication a semiconductor chip is very complex and usually requires a relatively long period of time, typically measured in months or years to complete. Like any other complex procedure, mistakes or anomalies may arise and prevent proper functionality. Any anomalies arising from fabrication, circuit design errors and oversights, and functional or logic errors must identified and corrected before the semiconductor chip is released for commercial use. The phase of the overall fabrication procedure during which these oversights and anomalies are identified and corrected is referred to as the xe2x80x9cdebugxe2x80x9d stage. It is essential that the design errors and fabrication anomalies be identified and corrected during the debug stage, because otherwise the IC will not achieve its intended functionality. Furthermore, until the errors are identified and understood, corrections may need to be made in the circuit design, the connectivity of the logic cells and/or the fabrication process, to eliminate the defects.
To identify the errors during the debug stage, it is typical to use testers which generate particular signals and combinations of signals that are applied to the fabricated IC, and to measure the response of the IC to these input stimulus signals. The responses are measured both at the output of the IC and internally at different connection points or nodes between the cells. The internal measurements are obtained either by the use of a mechanical probe which physically contacts a, node or by an electron beam device which projects an electron beam onto the node and derives an electrical signal from the electron beam. The signals derived from the actual IC are then compared to the computer tool-simulated signals at the comparable nodes of the simulated schematic circuit. If there is a discrepancy, that discrepancy indicates a problem in the fabrication or design of the IC. Thus, the typical previous approach to identifying the errors is to first obtain the actually-measured signals from the IC under the conditions which create the error, and then compare the actually-measured signals to the signals generated from a waveform simulation based on the circuit schematic.
The large number of very small cells within the typical IC complicates the task of tracing the signal within the IC. The task is made even more difficult by the difficulty in locating particular nodes and cells among the hundreds or thousands of such nodes and cells in a typical IC. Moreover, the task can be further complicated if the engineer or technician who is involved in conducting the tests did not design the circuit. Under such circumstances the test engineer is not as familiar with the circuit design as the design engineer, which further complicates the task and increases the possibility of further inadvertent errors.
Moreover, the complexity arising from the number and connectivity of the cells makes it a very time-consuming task to debug the IC. The debug process begins by identifying the particular circumstances or combination of input signals which create the error. The error is manifested in an erroneous output signal delivered from an output pad of the IC. Knowing the output error signal allows the test engineer to work backward into the preceding logic cells within the IC in an orderly, step-by-step manner to attempt to locate the cells or nodes within the IC which give rise to the error. The error may be caused by any of a series of components through which the preceding signals pass to influence the later-occurring signals and the output signals. Thus, viewed from the rear of the circuit looking forward into the preceding logic cells and nodes of the IC, there is an ever expanding segment or xe2x80x9cconexe2x80x9d of logic cells which are possible candidates for generating the error.
To trace a cone of logic cells, it is typical to trace the circuit schematic diagram and identify the logic cells which may have created the error. The tracing occurs manually, by employing mental steps used by the test and debug engineer, aided by the circuit diagram and waveform diagrams presented by the schematic viewing and waveform viewing tools. After identifying the logic cells and connection nodes of those logic cells, the output signal from each of the relevant logic cells is manually obtained from the comparable nodes and cells on the fabricated IC. After obtaining the measured signals, they are compared to the simulated signals. Any discrepancy points to the cause of the error. The complexity of the circuit prevents any other logical approach to identifying the errors, other than working backwards manually in a step-step-manner.
Days of time could be consumed in tracing the schematic diagram to identify the relevant components, collecting the measured signals from the IC, understanding the functionality of the circuit, and comparing the measured signals to the simulated signals. The task was complicated when the test engineer did not possess the same familiarity with the circuit schematic as did the original circuit designer. Such a circumstance sometimes occurs because of changes in personnel during the long time which can elapse between the circuit design phase of the IC and the fabrication phase of the IC. Furthermore, because of the complexity involved in the circuit and the necessity to use a manual, methodical and step-by-step approach to tracing the signals backwards through the circuit, it has been unproductive to guess or speculate as to the cause of an error without undertaking the step-by-step, methodical analysis. The number of components involved simply prevented any worthwhile shortcuts.
It is with respect to these and other considerations relevant to understanding the operation of debugging a modern IC that have given rise to the present invention.
One aspect of the present invention relates to a new and improved methodology for quickly identifying only those logic cells and their connectivity points or nodes within the IC which are relevant to the functionality or an error in the IC, which may arise at a particular instance of time during operation of the IC. As a result, a test engineer who is not thoroughly familiar with the circuit design is more competent to efficiently identify potential errors in logic cells and their connection nodes. Another aspect of the present invention allows particular logic cells and their connection nodes to be rapidly and automatically identified as a rearwardly-expanding group or cone of logic cells. Identifying a cone of logic cells and their connectivity in this manner avoids the problems of the test engineer manually and mentally making decisions based on the circuit schematic, and also allows the test engineer to skip or leapfrog levels of logic in an attempt to locate the error without methodically testing each of the logic cells and nodes in a manual, step-by-step, rearward manner. This feature minimizes the number of logic cells which must be considered, reduces the amount of time required for debugging or understanding the circuit, and reduces the tedium of tracing the logic cells and nodes backward in the schematic while minimizing the risks of errors resulting from the manual tracing process itself. Moreover, by quickly identifying the cone of logic cells and nodes which are relevant to the failure or error, it is not necessary to collect the actually-measured signals at each stage or level of cells and nodes. Only those signals at selected points need be obtained and compared to the simulated waveforms. Thus, the actual number of steps involved in debugging and understanding the circuit are potentially reduced. In general, the present invention facilitates a more rapid and efficient analysis of new semiconductor chips and circuits, and does so under circumstances where an extensive knowledge of the underlying circuit design is not required for efficient analysis.
To achieve these and other aspects, the present invention involves a method of identifying and displaying relevant ones of a plurality of connected logic cells and waveforms from the logic cells of a circuit. The method makes use of a circuit simulation tool to describe input and output waveforms to and from each logic cell and a transition of the waveforms and a transition time point when the transition occurs in each waveform. The steps of the method comprise selecting the output waveform and a transition time point of the selected output waveform delivered from a selected logic cell, identifying a predictive input waveform and a transition time of the predictive input waveform to the selected logic cell which causes the transition of the output signal from the selected logic cell at the selected transition time, and identifying a predictive logic cell connected to the selected logic cell which supplies the output waveform to the selected logic cell which constitutes the predictive input waveform previously identified. At least one new repetition of these three steps is performed under circumstances where the predictive logic cell identified in a previous repetition becomes the selected logic cell for the new repetition and the transition time point of the predictive input waveform to the selected logic cell of the previous repetition becomes the selected transition time of the output waveform of the selected logic cell for the new repetition.
Other preferred aspects and steps of the method of the present invention relate to displaying a schematic diagram of the selected and predictive logic cells identified from all of the repetitions, and displaying the input and output waveforms of the selected and predictive logic cells identified from the all of the repetitions, preferably by using a conventional schematic viewing tool and a conventional waveform viewing tool. The displayed schematic diagrams and waveform simulations are analyzed to gain an understanding of the circuit, and to identify defects in a practical embodiment of the circuit by comparing the actually measured signals to the simulated waveforms at the locations identified by the displayed schematic diagram.
The method also preferably relates to creating information describing the logic cells of the circuit by using information describing output waveforms from the logic cellsdescribed by the simulation tool. The information preferably describes the state of the output waveform at each output waveform transition and the time point of the output waveform transition for each logic cell, time delay information of the time delay between the occurrence of the predictive input waveform and the transition of the output waveform for each logic cell, the predictive input waveform and the transition time point of the predictive input waveform. The latter two items of information, and input predictor signal and an input predictor signal transition time, are preferably identified from the information describing the state of the output waveform at each output waveform transition and the time point of the output waveform transition for each logic cell, the time delay information associated with each selected and predictive logic cell, and the information describing the circuit.
Other preferred aspects of the present method involve selecting the number of repetitions, performing repetitions until the predictor input waveform is identified as a stimulus input waveform applied to the simulation tool, and performing repetitions until the identified predictive logic cell is a beginning logic cell of the circuit.
A further preferred aspect of the invention identifies the predictive input waveform as a synchronous waveform, such as a clock waveform. As a part of defining a cone of connected predictive and selected logic cells by performing the repetitions, the cone may include a sub-part which involves a synchronous logic cell which causes a synchronous waveform. In such a case, the the same type of repetitions are performed to define the sub-part of the cone.
Accomplishing the steps allows a chain or cone of logic cells to be identified automatically by using the input predictor signal, the input predictor signal transition time, the output state change signal and the output state change signal transition time. This information identifies the relevant ones or a cone of logic cells which are responsible for causing the output waveform transition at the selected time. The schematic and waveform viewing tools utilize this information to assemble the relevant schematic diagrams and waveform simulations. This assembled information facilitates a rapid and clear understanding of the functionality of the relevant logic cells, thereby avoiding the manual and time-consuming effort of individually identifying each logic cell by tracing through the schematic diagram, evaluating the waveform diagrams, and determining the next relevant logic cell in a series as a result of the waveform diagram evaluation. Instead, the automatic nature of the present invention rapidly displays the relevant logic cells and their simulated waveforms, thereby allowing the circuit analyst to focus on understanding circuit functionality rather than risking the diversion of a complete understanding of the circuit caused by manual tracing activities.